Vlsi physical design automation theory and practice pdf


 

Practical problems in VLSI physical design automation · Read more · VLSI Physical Design Automation: Theory and Practice. Read more. VLSI Physical Design Automation: Theory and Practice fills the void and is an essential introduction for senior undergraduates, postgraduates and anyone. It sounds good when knowing the vlsi physical design automation theory and practice in this website. This is one of the books that many people looking for.

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Vlsi Physical Design Automation Theory And Practice Pdf

VLSI physical design automation theory and practice. Material. Type. Book. Language English. Title. VLSI physical design automation theory and practice. Download as PDF, TXT or read online from Scribd. Flag for VLSI PHYSICAL. DESIGN AUTOMATION: Theory and Practice. Sadiq M. Sait Habib Youssef. a design engineer relies on software supplied by a CAD to the layout of random logic. The book concludes with a vendor to complete the design of the physical.

Solving discrete optimization problems with genetic algorithms is in many aspects di erent from the so- For solving discrete real-world optimization prob- lution of continuous problems. During the application crete and the search has to reach feasible points after of these operators, problem speci c knowledge can the application of the gentic operators. This can be be used to generate high quality o spring. Here achieved by the use of a problem speci c genotype in contrast to function optimization for example encoding, and hybrid, knowledge based techniques, bad genes, which would never be a building-block which support the algorithm during the creation of in a global optimal solution, could be recognized. In this paper a genetic algorithm for the that these bad genes are not included in the pop- layout generation of VLSI-chips is presented, which ulation by hill-climbing strategies, which could be optimizes two, usually consecutively solved tasks si- integrated in the construction of the initial individ- multaneously: together with the placement of the uals or during the application of the operators. In modules, the routes for the interconnection nets are opposite to this, one could not know the good genes, optimized. From this pool the algorithm can compose One of the main feature of a genetic algorithm ap- some good and hopefully eventually the optimal plied to an optimization problem is the fact, that solution to the given optimization problem. Thus the In the following, after a short description of the phys- genetic algorithm explores the space of these encod- ical design process of VLSI-chips, a problem speci c ings rather than the solution space itself. For contin- genetic algorithm for the layout generation is de- uous parameter optimization problems, both spaces scribed. This approach takes into account the pre- are identically. A straight-forward genotype encod- vious mentioned items by covering the following fea- ing in this case is a string of genes, which are simple tures: oats. Each gene represents an element of the vector de ning a point in the solution space.

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In the routing phase, pins Figure 1: The input for a xed cell top on the border of the modules have to be connected. The algorithm described in this paper combines the routing with the placement pro- A layout is described by the positions of the mod- cess during layout generation.

For a more detailed ules, the chosen implementation for the exible mod- description of the usual phases and possible solution ules and the routes of the interconnection nets on methods in contrast to the approach described in this the layout-surface between the cells.

A feasible way to characterize the placement of the modules is a binary slicing tree. This tree is the problem spe- ci c genotype encoding for the layout optimization cf. Each module represents a functional unit which consists of hierarchically arranged sub- cells. There are two kinds of modules cf.

For the interconnection nets of a exible module, only a list of terminals for each side is given but no exact termi- nal positions, because these vary with the di erent Figure 2: The genotype representation implementations. For that, a complete graph is con- by its leaves.

VLSI Physical Design Automation: Theory and Practice

Each inner node represents a meta- structed: the nodes represent the blocks, and each block, which de nes the arrangement for the set of edge is weighted with a value which de nes the qual- blocks characterized by the leaves of the correspond- ity of a meta-block consisting of the two blocks char- ing sub-tree and information about the routing in- acterized by the adjacent nodes.

A matching in this side this partial layout. All possible implementations graph is a set of disjunct node pairs and the max- for exible blocks are taken into account by storing imum weighted matching is the matching with the shape-functions for all nodes in the tree so that a maximal sum of edge weights cf.

The qual- single individual represents di erent layouts, if some ity of a meta-block is marked out by the number of blocks are exible. When combining two blocks to common nets of the combined blocks. Hence, the shape- functions of both blocks can be added which results in a shape-function for the meta-block.

For the example shown in gure 65 75 3, two exible blocks with three and two implemen- 80 tations are positioned upon. The shape-function for the resulting meta-block has only two di erent non redundant implementations. An upper bound for the routing space inside the meta-block is computed 60 and added to its shape-function. In the second iteration, meta-blocks which consist of two blocks are paired, in the third iteration meta-blocks with four blocks are combined, and so on.

This heuristic places highly connected blocks together and so re- Figure 3: The combination of two exible duces the overall wirelength and the total area of the blocks to a meta-block and the layout.

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Because the iterated matching is a determin- addition of routing space istic process, care has to be taken to create various individuals. For that, randomness is included in the computation of the edge weights for some of the used matching graphs. When choosing random routes Figure 5: The construction of the detailed for all nets out of the channels, many nets are routed routing when combining a meta- to the outer border of the layout and have to be con- block nected after composing the root node.

Note that a meta-block is considered to be a xed unit in the higher levels of the tree.

When combining two blocks, all routing inside the resulting meta-block is done cf. Ter- As mentioned before, all resulting implementations minals in the channel and on the outer sides of the for the meta-blocks containing exible blocks are blocks are connected, if they are shared by a com- stored. Storing all alternatives is useful because one mon net. Nets inside the channel which could not could not decide in the lower levels of the tree, which be connected or have to be connected to more termi- implementation of a meta-block would be the best to nals than only those contained in this meta-block are minimize the overall area of the layout.

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